1. Field of the Invention
The embodiments of the invention generally relate to lithographic patterning of semiconductor wafers and, more particularly, to a method for lithographically patterning semiconductor wafers using a combination of photolithographic and copolymer self-assembling lithographic techniques.
2. Description of the Related Art
Currently, in the field of lithographic patterning conventional photolithographic techniques can only be used to achieve feature dimensions in the 70-100 nm range. To overcome the limitations of conventional photolithographic techniques, self-assembling copolymer lithographic techniques were developed that can be used to form useful periodic patterns with molecular dimensions in the 20-40 nm range (e.g., see “Self-assembling resists for nanolithography” by Nealey et al., Electron Devices Meeting, 2005. IEDM Technical Digest, IEEE International, December 2005 and U.S. Pat. No. 6,746,825 of Nealy et al. issued on Jun. 8, 2004, which are incorporated herein by reference). Self-assembling copolymer lithographic techniques generally include using exposure tools to define a periodic chemical pattern in a substrate such that adjacent sections of the substrate have contrasting chemical functionalities and dimensions of less than 40 nm. This can be accomplished because, while imaging materials are only able to resolve patterns in the 70-100 nm range, exposure tools are able to resolve patterns having dimensions of 20 nm or even less. Next, a copolymer mixture is applied to the substrate surface and then annealed. During the anneal process, different block polymers interact differently with the contrasting chemical functionalities in the substrate such that they are re-arranged to form a regular periodic pattern of discrete block polymer sections that are registered with and perpendicular to the periodic chemical pattern in the substrate. Different block polymer sections can be selectively removed, thereby creating a developed pattern that can subsequently be transferred into the substrate. This self-assembly copolymer lithographic technique has been used to create uniform periodic patterns with molecular dimensions over very large surface areas, e.g., in order to form magnetic domains for hard drive disks.
Unfortunately, this self-assembly copolymer technique is currently not suitable for use in next generation complementary metal oxide semiconductor (CMOS) technology because of the need for precise registration and overlay capabilities. Specifically, 45/32 nm node CMOS technology requires sub-50 nm metal contacts in order to connect transistors to back end of the line (BEOL) wiring. However, current 0.93NA photolithography tools can only print patterns that can be used to form 100 nm contacts. Furthermore, next generation photolithograph tools (e.g., 1.2NA immersion photolithography tools) are only expected to print patterns that can be used to form 70-80 nm contacts. These larger contact sizes (e.g., 70 nm or greater) contribute to a lower than desirable device density on each chip. Thus, there is a need in the art for a technique for printing patterns that can be used to form structures (e.g., contacts, interconnects, device components, etc.), having less than 50 nm dimensions, on semiconductor wafers. However, the technique must also be able provide precise registration and overlay capabilities to ensure exact placement of the sub-50 nm structures relative to the position of one or more previously formed structures within the wafer substrate.